Session 10 - The Next Waves of Machine and Deep Learning Hardware
1.
S: 10-1 Design Considerations for Deep Learning Hardware Acceleration
(Author:  Leland Chang, IBM)

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2.
S: 10-2  Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks
(Author: Vivienne Sze, MIT)

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3.
S: 10-3  Training Deep Neural Networks on a Reconfigurable Non-Von Neumann Computer Architecture,
(Author: Chris Nicol, Wave Computing)

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4.
S: 10-4  Narrowing the Computational Efficiency Gap Between Artificial and Natural Intelligence
(Author: Anand Raghunathan, Purdue)

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5.
S: 10-5  Mixed-Signal Nanoelectronic Neurocomputing
(Author: Dmitri Strukov, UCSB)

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