Session 2 - Wireline Techniques for Advanced Modulation Schemes
1.
S: 2-1 High-Speed Contactless I/O for Computing Devices (Invited)
(Authors: C. Thakkar, J. Jaussi, B. Casper, Intel Corporation)

 5 (best) 
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2.
S: 2-2  A Process and Temperature Insensitive CMOS Linear TIA for 100 Gbps PAM-4 Optical Links
(Authors: Kadaba Lakshmikumar, Alexander Kurylak, Manohar Nagaraju, Richard Booth, Joe Pampanin, Cisco Systems)

 5 (best) 
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3.
S: 2-3  A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE, (Outstanding Student Paper Nominee)
(Authors: S. Kiran, S. Cai, Y. Luo, S. Hoyos, S. Palermo, Texas A&M University)

 5 (best) 
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4.
S: 2-4  A 56 Gb/s PAM4 Receiver with Low-Overhead Threshold and Edge-Based DFE FIR and IIR-Tap Adaptation in 65nm CMOS, (Outstanding Student Paper Nominee),
(Authors: A. Roshan-Zamir, T. Iwai, Y.-H. Fan, A. Kumar, H. W. Yang, L. Sledjeski*, J. Hamilton*, S. Chandramouli*, A. Aude*, S. Palermo, Texas A&M University, *Texas Instruments Corporation  )

 5 (best) 
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