Session 9 - High Performance Oscillators and Low-Power Digital Clock Generation
1.
S: 9-1 A Noise Circulating Cross-Coupled VCO with a 195.6dBc/Hz FoM and 50kHz 1/f3 Noise Corner, (Outstanding Student Paper Nominee)
(Authors: F. Wang, H. Wang, Georgia Institute of Technology)

 5 (best) 
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2.
S: 9-2 Low Noise RF Quadrature VCO Using Tail-Switch Network-Based Coupling in 40 nm CMOS
(Authors: Venkatraman Natarajan, Mohammadhossein Naderi Alizadeh, Jose Silva-Martinez, Texas A&M University)

 5 (best) 
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3.
S: 9-3 A 1.2ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique
(Authors: Bangan Liu, Huy Cu Ngo,  Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada and Akira Matsuzawa, Tokyo Institute of Technology)

 5 (best) 
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4.
S: 9-4 A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS
(Authors:Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, University of Illinois at Urbana-Champaign)

 5 (best) 
Presentation Quality
Technical Quality
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