Session 20 - Oversampling AID Converters
1.
S: 20-1 Finite-Impulse-Response (FIR) Feedback in Continuous-Time Delta-Sigma Converters (Invited), (Outstanding Invited Paper Nominee)
(Author: S.Pavan, Indian Institute of Technology, Madras  )

 5 (best) 
Presentation Quality
Technical Quality
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2.
S: 20-2 An 85MHz-BW 68.5dB-SNDR ASAR-Assisted CT 4-0 MASH Delta Sigma Modulator with Half-Range Dithering-Based DAC Calibration in 28nm CMOS
(Authors: H. Liu, G. Gielen, KU Leuven, X. Xing, Tsinghua University)

 5 (best) 
Presentation Quality
Technical Quality
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3.
S: 20-3 A 1V 175uW 94.6dB SNDR 25kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
(Authors: Sheng-Hui Liao,Jieh-Tsorng Wu, National Chiao Tung University )

 5 (best) 
Presentation Quality
Technical Quality
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4.
S: 20-4 A Continuous-Time Delta-Sigma Modulator with Self-ELD Compensated Quantizer
(Authors: C. Han, T. Kim*, and N. Maghari, University of Florida, *Now with Microchip Technology Inc.)

 5 (best) 
Presentation Quality
Technical Quality
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5.
S: 20-5 A 200MHz-BW 0.13mm2 62dB-DR VCO-Based Non-Uniform Sampling ADC with Phase-Domain Level Crossing in 65nm CMOS, (Outstanding Student Paper Nominee)
(Authors: Tzu-Fan Wu, Mike Shuo-Wei Chen, University of Southern California)

 5 (best) 
Presentation Quality
Technical Quality
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6.
S: 20-6 A 1 MHz Bandwidth, Filtering Continuous-Time Delta-Sigma ADC with 36 dBFS Out-of-Band IIP3 and 76 dB SNDR
(Authors: S.Manivannan , S.Pavan, IIT Madras)

 5 (best) 
Presentation Quality
Technical Quality
  • Comment:

  • 500 characters left.