Session 21 - Timing Techniques
1.
S: 21-1 A 0.008mm2 2.4GHz Type-I Sub-Sampling Ring-Oscillator-based Phase-Locked Loop with a -239.7dB FoM and -64dBc Reference Spurs, (Outstanding Student Paper Nominee)
(Authors: Shravan S. Nagam, Peter R. Kinget, Columbia University)

 5 (best) 
Presentation Quality
Technical Quality
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  • 500 characters left.
2.
S: 21-2 A 46uW, 8.2MHz Self-threshold-tracking Differential Relaxation Oscillator with 7.66psrms Period Jitter and 1.56ppm Allan Deviation Floor
(Authors: Shao-Lung Lu, Yu-Te Liao, National Chiao Tung University)

 5 (best) 
Presentation Quality
Technical Quality
  • Comment:

  • 500 characters left.
3.
S: 21-3 A 350-mV, Under-200-ppm Allan Deviation Floor Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
(Authors: A. Kobayashi*, Y. Nishio*, K. Hayashi*, K. Nakazato*, K. Niitsu* **, *Nagoya University, **JST/PRESTO)

 5 (best) 
Presentation Quality
Technical Quality
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4.
S: 21-4 A 78.2nW 3-Channel Time-Delay-to-Digital Converter using Polarity Coincidence for Audio-based Object Localization
(Authors: Daniel de Godoy, Xiaofan Jiang and Peter R. Kinget, Columbia University)

 5 (best) 
Presentation Quality
Technical Quality
  • Comment:

  • 500 characters left.